Leakage Power Reduction with Various IO Standards and Dynamic Voltage Scaling in Vedic Multiplier on Virtex-6 FPGA
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DOI:
https://doi.org/10.17485/ijst/2016/v9i25/134930Keywords:
HSTL, IO Standards, LVCMOS, SSTL, Static Power Reduction, Vedic Multiplier, Voltage Scaling.Issue & Section & Categories
Volume 9, Issue 25, July 2016 ||
Articles
How to Cite
Pandey, B., Rahman, M. A., Hussain, D. M. A., Saxena, A., & Das, B. (2016). Leakage Power Reduction with Various IO Standards and Dynamic Voltage Scaling in Vedic Multiplier on Virtex-6 FPGA. Indian Journal of Science and Technology, 9(25). https://doi.org/10.17485/ijst/2016/v9i25/134930
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