Energy Efficient CRC Design for Processor of Workstation, and Server using LVCMOS
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DOI:
https://doi.org/10.17485/ijst/2017/v10i4/139586Keywords:
40 nm FPGA, CRC, Energy Efficient, Low Power, LVCMOS IO Standard.Issue & Section & Categories
Volume 10, Issue 4, January 2017 ||
Articles
How to Cite
Saxena, A., Patel, C., & Sadiq Ali Khan, M. (2017). Energy Efficient CRC Design for Processor of Workstation, and Server using LVCMOS. Indian Journal of Science and Technology, 10(4). https://doi.org/10.17485/ijst/2017/v10i4/139586
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